A. Field of the Invention
This invention relates to high speed cyclic memories, and more particularly to a high speed check of the accuracy of the data written therein.
B. Description of the Prior Art
In digital data handling systems, data is transferred at high speed and in parallel. However, where data is transferred over communication lines, usually in serial fashion, the transfer rate is relatively slow and not matched to the high speed of the data handling system. Therefore, buffers are used to accumulate small portions of slow incoming data and supply it at high rates to the receiving system, normally to the memory of the receiving system. Once the portion of the data is supplied to the receiving system, the buffer is available to accumulate another portion of the slow incoming data. As the further incoming data its accumulated, it destroys the previous portion of the data.
Should the high speed transfer of the previous portion of the data result in an error which was not detected until further incoming data is accumulated, the previous data could not be retransferred from the buffer to correct the error, and the data would be lost. Only a slow, time-consuming retransmission of the data from the originating source would recover the lost data.
A prior attempt at solving this problem comprised the use of extensive error correcting codes that accompany the data and are devised to correct the most likely occurring errors. However, to be useful and actually correct nearly all such errors, the added code data calculated in accordance with the codes and supplied along with the data is considerable, often ten percent of the original data and sometimes more. The addition of so much code data can be both time-consuming and uneconomical.